VLSI Auto Layout Generator

CAD tool ----Automatic Layout Generator

Developer: Yu Zhang (zhangyu7788@gmail.com)

Created Time: 10/2010~11/2010
Organization: Syracuse University L.C. Smith College

Intro:

This is a CAD tool, which takes a complex Boolean function as the input, and automatically generates the physical layout of the complex gate with minimized overall area.

Developed in native C++ and managed C++ (total 2,500 lines of codes). Winform is applied to develop the UI.

First approach to reduce the overall area: design complex gate

What is complex gate?

Complex gate is a circuit that implements complex Boolean function (like Y=~(A+(B*C)+(D*E))) directly by means of NMOS and PMOS transistors, rather than by conventional primitive elements like NAND, NOR, NOT and XOR gates.

Why could complex gate reduce area?

For example, in a function like Y=~(A+(B*C)), an AND gate and a NOR gate are needed. An AND gate is usually implemented as a NAND gate plus an inverter. These three components are separated, which obviously increase the overall area because of the required space among them.

Second approach to reduce area: rearrange polysilicon

Physically adjacent transistors can be connected by a diffusion area, instead of using metals. If it can be done at the same column of both NMOS part and PMOS part, the overall area can be reduced. If there is no connection between physically adjacent transistors, separations are required. By rearranging polysilicons, we try to place as many logically connected transistors as possible to be physically adjacent so that diffusion gaps are minimized.

Third approach to reduce area: follow design rule, and choose minimally required spacing

All the design follows SCMOS Sub-micron design rule and is costumed with minimal spacing between layers.